package pufsim
 
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import firrtl.options.TargetDirAnnotation

import pufsim._

object verilog_topsim extends App {
    (new chisel3.stage.ChiselStage).execute(
        Array("-X", "verilog", "--full-stacktrace"),
        Seq(ChiselGeneratorAnnotation(() => new top()),
        // TargetDirAnnotation("/home/zhangshen/workspace/PUF/projects/puf/vsrc"))
        TargetDirAnnotation("generated/puf_sim/"))
    )
}

// sbt "test:runMain pufsim.verilog_topsim"
// cp ./generated/puf_sim/top.v ../projects/puf_sim/vsrc/top.v